1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a non-volatile memory array.
2. Description of Related Art
Electrically erasable programmable read only memory (EEPROM) is one type of non-volatile memory that allows multiple data writing, reading and erasing operations. Furthermore, the stored data will be retained even after power to the device is removed. With these advantages, EEPROM has been broadly applied in personal computer and electronic equipment.
A conventional EEPROM has a floating gate and a control gate, which are manufactured by doped polysilicon. Such non-volatile memory is having a double layer gate which is hard to integrate with general CMOS Logic Process. Furthermore, the fabricating cost of the whole embedded non-volatile memory increases due to the double layer gate which is unfavorable in competition at an advantageous position.
In addition, when programming the memory, the electrons are injected into the floating gate and uniformly distributed in the whole polysilicon floating gate layer. However, if the tunneling oxide layer under the polysilicon floating gate layer has defects, it can easily cause a leakage current of the device, affecting the reliability of the device.
In order to solve the problem of the leakage current of the EEPROM device, a charge trapping material is adopted to replace the polysilicon. Such charge trapping material is silicon nitride, for example. Since the silicon nitride has capable of trapping electrons, the electrons injected into the silicon nitride layer just concentrate in local region, it is not so sensitive to the defects of the tunneling oxide layer, and thus lessening the leakage current of the device. The silicon nitride layer usually has a silicon oxide layer on its top surface and bottom surface respectively, thus forming an oxide-nitride-oxide (ONO) composite layer.
On the other hand, in order to prevent the problem of data error due to over-erase/write phenomenon when the typical EEPROM erases/writes, a select transistor serially connected at one side of the memory cells to form the two transistors (2T) structure. The programming and reading of the memory cells can be controlled by the select transistor.
A memory unit of the aforementioned 2T structure is serially connected by a select transistor and a memory cell. A bit line is connected next to the memory cell and a source line is connected next to the select transistor. While operating the non-volatile memory array having the 2T structure, the unselected memory unit connected with the selected bit line of the selected memory unit might have the situation of program disturb or erase disturb which cause the memory unit to be mistakenly written or erased. For example, when performing programming operation by channel hot carrier injection, a high voltage is applied to the bit line of the selected memory unit because the bit lines in the same row are connected together; namely, all memory units in the same row effect by the program disturb. When performing erasing operation by Fowler-Nordheim (FN) tunneling effect, a high voltage is applied to the bit line of the selected memory unit because the bit lines in the same row are connected together. One high voltage is cross between the control line and the bit line and cause all memory units to generate the soft erasure and to lower the reliability of the memory unit.